CY29948

2.5 V or 3.3 V, 200-MHz,

1:12 Clock Distribution Buffer

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 38-07288 Rev. *E

Revised May 2, 2011

2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer

Features

Description

The CY29948 is a low-voltage 200-MHz clock distribution buffer

with the capability to select either a differential LVPECL or a

LVCMOS/LVTTL compatible input clock. The two clock sources

can be used to provide for a test clock as well as the primary

system clock. All other control inputs are LVCMOS/LVTTL

compatible. The 12 outputs are LVCMOS or LVTTL compatible

and can drive 50

series or parallel terminated transmission

lines. For series terminated transmission lines, each output can

drive one or two traces giving the device an effective fanout of

1:24. The outputs can also be three-stated via the three-state

input TS#. Low output-to-output skews make the CY29948 an

ideal clock distribution buffer for nested clock trees in the most

demanding of synchronous systems.

The CY29948 also provides a synchronous output enable input

for enabling or disabling the output clocks. Since this input is

internally synchronized to the input clock, potential output

glitching or runt pulse generation is eliminated.

Block Diagram

PECL_CLK

PECL_CLK#

0

1

TCLK

TCLK_SEL

SYNC_OE

TS#

VDD

VDDC

12

Q0-Q11

Pin Configuration

CY29948

VSS

Q4

VDDC

Q5

VSS

Q6

VDDC

Q7

TCLK_SEL

TCLK

PECL_CLK

PECL_CLK#

SYNC_OE

TS#

VDD

VSS

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

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