 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC24F04KA201 Datasheet(PDF) 22 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC24F04KA201 Datasheet(HTML) 22 Page - Microchip Technology |
|
|
22 / 26 page  PIC24FXXKA2XX DS39991A-page 22 2010 Microchip Technology Inc. 5.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS TABLE 5-1: STANDARD OPERATING CONDITIONS Standard Operating Conditions Operating Temperature: 0 C to +70C and programming: +25C is recommended. Param No. Symbol Characteristic Min Max Units Conditions D111 VDD Supply Voltage During Programming VDDCORE 3.60 V Normal programming D112 IPP Programming Current on MCLR —50 A— D113 IDDP Supply Current During Programming — 2 mA — D031 VIL Input Low Voltage VSS 0.2 VDD V— D041 VIH Input High Voltage 0.8 VDD VDD V— D042 VIHH Programing Voltage on VPP VDD +1.5 9 V — D080 VOL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6V D090 VOH Output High Voltage 1.4 — V IOH = -3.0 mA @ 3.6V D012 CIO Capacitive Loading on I/O Pin (PGDx) — 50 pF To meet AC specifications P1 TPGC Serial Clock (PGCx) Period 125 — ns — P1A TPGCL Serial Clock (PGCx) Low Time 50 — ns — P1B TPGCH Serial Clock (PGCx) High Time 50 — ns — P2 TSET1 Input Data Setup Time to Serial Clock 15 — ns — P3 THLD1 Input Data Hold Time from PGCx 15 — ns — P4 TDLY1 Delay Between 4-Bit Command and Command Operand 40 — ns — P4A TDLY1A Delay Between 4-Bit Command Operand and the Next 4-Bit Command 40 — ns — P5 TDLY2 Delay Between Last PGCx of Command Byte and First PGCx of Read of Data Word 20 — ns — P6 TSET2VDD Setup Time to MCLR 100 — ns — P7 THLD2 Input Data Hold Time from MCLR VPP (from VIHH to VIH) 25 — ms — P10 TDLY6 PGCx Low Time After Programming 400 — ns — P11 TDLY7 Chip Erase Time 5 — ms — P12 TDLY10 Page (4 rows) Erase Time 5 — ms — P13 TDLY9 Row Programming Time 2 — ms — P14 TR MCLR Rise Time to Enter ICSP™ mode — 1.0 s— P15 TVALID Data Out Valid from PGCx 10 — ns — P16 TDLY10 Delay Between Last PGCx and MCLR 0— s — P17 THLD3MCLR to VDD —100 ns — P18 TKEY1 Delay Between First MCLR and First PGCx for Key Sequence on PGDx 1— ms — P19 TKEY2 Delay Between Last PGCx for Key Sequence on PGDx and Second MCLR 1— ms — |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
