PCF2129A datasheet(31/69 Pages) NXP

31 / 69 page

PCF2129A_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 7 May 2010

31 of 69

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

8.10.3 Watchdog timer function

The watchdog timer function is enabled or disabled by the WD_CD bit of the register

Watchdg_tim_ctl (see Table 30).

The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock

frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1

⁄

60 Hz (see Table 32).

When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val

(see Table 32) determines the watchdog timer period.

The watchdog timer counts down from the software programmed 8-bit binary value n in

(register Control_2) is set logic 1 and an interrupt will be generated.

The counter does not automatically reload.

When WD_CD is logic 0 (watchdog timer disabled) and the microcontroller unit (MCU)

loads a watchdog timer value n, then:

• the flag WDTF is reset

• INT is cleared

• the watchdog timer starts again

Loading the counter with 0 will:

• reset the flag WDTF

• clear INT

• stop the watchdog timer

Remark: WDTF is read only and cannot be cleared with the interface. WDTF can be

cleared by:

• loading a value in register Watchdg_tim_val

• reading of the register Control_2

Writing a logic 0 or logic 1 to WDTF has no effect.

Table 32.

Programmable watchdog timer

TF[1:0]

Timer source

clock frequency

Units

Minimum timer

period (n = 1)

Units

Maximum timer

period (n = 255)

Units

4.096

kHz

244

μs

62.256

15.625

3.984

255

⁄

15300

PCF2129A Datasheet(PDF) 31 Page - NXP Semiconductors

PCF2129A Datasheet(HTML) 31 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL