TMS320F2812 datasheet(36/170 Pages) TI

36 / 170 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S – APRIL 2001 – REVISED MARCH 2011

www.ti.com

Table 3-5. Impact of Using the Code Security Module

CODE SECURITY STATUS

ADDRESS

Code Security Enabled

Code Security Disabled

0x3F 7F80 – 0x3F 7FEF

Fill with 0x0000

Application code and data(1)

0x3F 7FF0 – 0x3F 7FF5

0x3D 7BFC – 0x3D 7BFF

Application code and data

(1)

See the TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature

number SPRZ193) for some restrictions.

Disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED

TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY

(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN

ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO

TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR

THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE

COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED

MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT

AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS

CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED

WARRANTIES OF MERCHANT ABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,

INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY

OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,

BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR

INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

3.2.12 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The

PIE block can support up to 96 peripheral interrupts. On the F281x and C281x, 45 of the possible

96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed

into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector

stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched

by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical

CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is

controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE

block.

3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI)

The F281x and C281x support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with

one non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the

interrupts can be selected for negative or positive edge triggering and can also be enabled/disabled

(including the XNMI). The masked interrupts also contain a 16-bit free-running up-counter, which is reset

to zero when a valid interrupt edge is detected. This counter can be used to accurately time-stamp the

interrupt.

Functional Overview

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2812 Datasheet(PDF) 36 Page - Texas Instruments

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