CY14B101KA datasheet(21/34 Pages) CYPRESS

Part #	CY14B101KA

Description	1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock

PDF	34 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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21 / 34 page

CY14B101KA

CY14B101MA

Document #: 001-42880 Rev. *I

Page 21 of 34

Figure 8. SRAM Read Cycle #2 (CE and OE Controlled) [30, 31, 32]

Figure 9. SRAM Write Cycle #1 (WE Controlled) [30, 32, 33, 34]

Switching Waveforms (continued)

Address Valid

Address

Data Output

Output Data Valid

Standby

Active

High Impedance

BHE, BLE

HZCE

ACE

LZCE

DOE

LZOE

DBE

LZBE

HZBE

HZOE

Data Output

Data Input

Input Data Valid

High Impedance

Address Valid

Address

Previous Data

SCE

PWE

HZWE

LZWE

BHE, BLE

Note

30. BHE and BLE are applicable for × 16 configuration only.

31. WE must be HIGH during SRAM read cycles.

32. HSB must remain HIGH during read and write cycles.

33. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

34. CE or WE must be

VIH during address transitions.

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