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IS0-1845ASRH/Sample Datasheet(PDF) 3 Page - Intersil Corporation

Part # IS0-1845ASRH/Sample
Description  Single Event Radiation Hardened High Speed, Current Mode PWM
PDF  3 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

IS0-1845ASRH/Sample Datasheet(HTML) 3 Page - Intersil Corporation

  IS0-1845ASRH/Sample Datasheet HTML 1Page - Intersil Corporation IS0-1845ASRH/Sample Datasheet HTML 2Page - Intersil Corporation IS0-1845ASRH/Sample Datasheet HTML 3Page - Intersil Corporation  
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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9001.4
September 25, 2008
Die Characteristics
DIE DIMENSIONS
3090µm x 4080µm (121.6 mils x 159.0 mils)
Thickness: 483µm ± 25.4µm (19 mils ± 1 mil)
INTERFACE MATERIALS
Glassivation
Type: Phosphorus Silicon Glass (PSG)
Thickness: 8.0kA ± 1.0kA
Top Metallization
Type: AlSiCu
Thickness: 16.0kA ± 2kA
Substrate
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish
Silicon
ASSEMBLY RELATED INFORMATION
Substrate Potential
Unbiased (DI)
ADDITIONAL INFORMATION
Worst Case Current Density
<2.0 x 105 A/cm2
Transistor Count
582
Metallization Mask Layout
IS-1845ASRH
NOTES:
3. Both the GND pads must be bonded to ground.
4. The OUT double-sized bond pad must be double bonded for
current sharing purposes.
5. The OSCGND double-sized bond pad must be double bonded to
ground for current sharing purposes.
VFB
COMP
VREF
VC
VCC
OUT
GND
GND
OSCGND
RTCT
ISENSE
IS-1845ASRH



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