GS7025 PRO-LINX™ Serial Digital Receiver

Data Sheet

13813 - 7

October 2009

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3.2.1.1 VCO

The VCO is a differential low phase noise, factory trimmed oscillator that provides

increased immunity to PCB noise and precise control of the VCO centre frequency. The

VCO has a pull range of ±15% about the centre frequency. A single low-impedance

external resistor, RVCO, sets the VCO centre frequency. The low-impedance RVCO

minimizes thermal noise and reduces the PLL's sensitivity to PCB noise.

The recommended RVCO value for SMPTE 259M-C applications is 365Ω.

When the input data stream is removed for an excessive period of time (see AC electrical

characteristics table), the VCO frequency can drift from the 270Mb/s centre frequency

to the limits shown in Table 3-1.

3.2.1.2 Phase Detector

The phase detector compares the phase of the PLL clock with the phase of the incoming

data signal and generates error correcting timing pulses. The phase detector design

provides a linear transfer function which maximizes the input jitter tolerance of the PLL.

3.2.1.3 Charge Pump

The charge pump takes the phase detector output timing pulses and creates a charge

packet that is proportional to the system phase error. A unique differential charge pump

design insures that the output phase does not drift when data transitions are sparse. This

makes the GS7025 ideal for SMPTE 259M-C applications where pathological signals

have data transition densities of 0.05.

3.2.1.4 Loop Filter

The loop filter integrates the charge pump packets and produces a VCO control voltage.

The loop filter is comprised of three external components which are connected to pins

LF+, LFS, and LF-. The loop filter design is fully differential giving the GS7025 increased

immunity to PCB board noise.

The loop filter components are critical in determining the loop bandwidth and damping

of the PLL. Recommended values for SMPTE 259M-C applications are shown in the

GS7025 Typical Application Circuit. No further changes from the recommended GS7025

loop filter components are necessary. For more information on choosing loop filter

component values, refer to the PLL DESIGN GUIDELINES section of the GS9025A data

sheet.

Table 3-1: Frequency Drift Range

Frequency

Min (%)

Max(%)

270Mb/s lock

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