FM21L16 - 128Kx16 FRAM

Rev. 2.0

Apr. 2011

Page 3 of 15

Functional Truth Table

1,2

/CE

/WE

A(16:2)

A(1:0)

/ZZ

Operation

X

X

X

X

L

Sleep Mode

H

X

X

X

H

Standby/Idle

↓

H

V

V

H

Read

L

H

No Change

Change

H

Page Mode Read

L

H

Change

V

H

Random Read

↓

L

V

V

H

/CE-Controlled Write

L

↓

V

V

H

L

↓

No Change

V

H

↑

X

X

X

H

Starts Precharge

Notes:

1)

H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care.

2)

/WE-controlled write cycle begins as a Read cycle and A(16:2) is latched then.

3)

Addresses A(1:0) must remain stable for at least 10 ns during page mode operation.

4)

For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.

Byte Select Truth Table

/WE

/OE

/LB

/UB

Operation

H

H

X

X

Read; Outputs Disabled

X

H

H

H

L

H

L

Read upper byte; Hi-Z lower byte

L

H

Read lower byte; Hi-Z upper byte

L

L

Read both bytes

L

X

H

L

Write upper byte; Mask lower byte

L

H

Write lower byte; Mask upper byte

L

L

Write both bytes

Note: Assumes /CE is low and /ZZ is high for all cases. The /UB and /LB pins may be

grounded if 1) the system does not perform byte writes and 2) the device is not

configured as a 256Kx8.

Figure 2. Simplified Sleep/Standby State Diagram