FM24V02 datasheet(3/16 Pages) RAMTRON

3 / 16 page

FM24V02 - 256Kb I2C FRAM

Rev. 2.0

May 2010

Page 3 of 16

Overview

The FM24V02 is a family of serial F-RAM memory

devices. The memory array is logically organized as a

32,768 x 8 bit memory array and is accessed using an

industry standard two-wire (I2C) interface. Functional

operation of the F-RAM is similar to serial

EEPROM. The major difference between the

FM24V02 and serial EEPROM is F-RAM’s superior

write performance.

Memory Architecture

When accessing the FM24V02, the user addresses

32,768 locations each with 8 data bits. These data bits

are shifted serially. The 32,768 addresses are

accessed using the two-wire protocol, which includes

a slave address (to distinguish other non-memory

devices) and a 2-byte address. All 15 address bits are

used by the decoder for accessing the memory.

The access time for memory operation is essentially

zero beyond the time needed for the serial protocol.

That is, the memory is read or written at the speed of

the two-wire bus. Unlike an EEPROM, it is not

necessary to poll the device for a ready condition

since writes occur at bus speed. That is, by the time a

new bus transaction can be shifted into the part, a

write operation will be complete. This is explained in

more detail in the interface section below.

Users expect several obvious system benefits from

the FM24V02 due to its fast write cycle and high

endurance as compared with EEPROM. However

there are less obvious benefits as well. For example

in a high noise environment, the fast-write operation

is less susceptible to corruption than an EEPROM

since it is completed quickly. By contrast, an

EEPROM requiring milliseconds to write is

vulnerable to noise during much of the cycle.

Note that it is the user’s responsibility to ensure that

VDD is within datasheet tolerances to prevent

incorrect operation.

Two-wire Interface

The FM24V02 employs a bi-directional two-wire bus

protocol using few pins or board space. Figure 2

illustrates a typical system configuration using the

FM24V02 in a microcontroller-based system. The

industry standard two-wire bus is familiar to many

users but is described in this section.

By convention, any device that is sending data onto

the bus is the transmitter while the target device for

this data is the receiver. The device that is controlling

the bus is the master. The master is responsible for

generating the clock signal for all operations. Any

device on the bus that is being controlled is a slave.

The FM24V02 always is a slave device.

The bus protocol is controlled by transition states in

the SDA and SCL signals. There are four conditions

including start, stop, data bit, or acknowledge. Figure

3 illustrates the signal conditions that specify the four

states. Detailed timing diagrams are shown in the

electrical specifications section.

Microcontroller

SDA

SCL

FM24V02

A0 A1 A2

SDA

SCL

FM24V02

A0 A1 A2

VDD

Rmin = 1.1 Kohm

Rmax = tR/Cbus

Figure 2. Typical System Configuration

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