FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011

Page 13 of 26

0Ch

Event Counter Control

D7

D6

D5

D4

D3

D2

D1

D0

-

-

-

-

RC

CC

C2P

C1P

RC

Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the

values without missing count events. The RC bit will be automatically cleared.

CC

Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by

C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of

Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is

“don‟t care” when CC=1. Battery-backed, read/write.

C2P

CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P is “don‟t care” when CC=1. The value

of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write.

C1P

CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. The value of Event Counter 1 may

inadvertently increment if C1P is changed. Battery-backed, read/write.

0Bh

Companion Control

D7

D6

D5

D4

D3

D2

D1

D0

SNL

FOEN

FC

WP1

WP0

VBC

VTP1

VTP0

SNL

Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only.

SNL cannot be

cleared once set to 1.

Nonvolatile, read/write.

FOEN

32.768kHz Frequency Output Enable. Default is 1 = “On”. Output FOUT turned off when FOEN = 0.

Temperature compensation is not applied to the 32.768kHz frequency on the FOUT pin.

FC

Fast Charge: Setting FC to „1‟ (and VBC=1) causes a ~1 mA trickle charge current to be supplied on V

Clearing VBC to „0‟ disables the charge current. Nonvolatile, read/write.

WP1-0

Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write.

Write protect addresses

WP1 WP0

None

0

0

Bottom ¼

0

1

Bottom ½

1

0

Full array

1

1

VBC

VBAK Charger Control. Setting VBC to 1 causes ~80 µA (FC=0) trickle charge current to be supplied on VBAK.

Clearing VBC to 0 disables the charge current. Nonvolatile, read/write.

VTP1-0

VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write.

VTP

VTP1

VTP0

2.6V

0 0

2.9V

0 1

3.9V

1 0

4.4V

1 1

0Ah

Watchdog Control

D7

D6

D5

D4

D3

D2

D1

D0

WDE

-

-

WDT4

WDT3

WDT2

WDT1

WDT0

WDE

Watchdog Enable. When WDE=1, a watchdog timer fault will cause the /RST signal to go active. When WDE = 0

the timer runs but has no effect on /RST, however the WTR flag will be set when a fault occurs. Note as the timer

is free-running, users should restart the timer using WR3-0 prior to setting WDE=1. This assures a full watchdog

timeout interval occurs. Nonvolatile, read/write.

WDT4-0

Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog

timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write.

Watchdog timeout

WDT4 WDT3 WDT2 WDT1 WDT0

Invalid – default 100 ms

0

0

0

0

0

100 ms

0

0

0

0

1

200 ms

0

0

0

1

0

300 ms

0

0

0

1

1

.

.

.

2000 ms

1

0

1

0

0

2100 ms

1

0

1

0

1

2200 ms

1

0

1

1

0

.