HT1647A

Rev. 1.40

13

April 29, 2011

PATENTED

V R

*

*

R

V S S

V 2

V 3

V 4

V 1

1 / 5 b i a s

R

V S S

V 2

V 3

V 4

V 1

1 / 4 b i a s

R

R

R

R

R

R

R

R

V D D

V L C D

V D D

V L C D

* T h e v o l t a g e a p p l i e d t o V L C D p i n m u s t b e e q u a l t o o r l o w e r t h a n V D D .

*

V R

*

Internal Resistor Type Bias Generator Configurations

Interfacing

Only six lines are required to interface with the

HT1647A. The CS line is used to initialize the serial in-

terface circuit and to terminate the communication be-

tween the host controller and the HT1647A. If the CS pin

is set to 1, the data and command issued between the

host controller and the HT1647A are first disabled and

then initialized. Before issuing a mode command or

mode switching, a high level pulse is required to initial-

ize the serial interface of the HT1647A. The DB0~DB3

are the 4-bit parallel data input/output lines. Data to be

read or written or commands to be written have to pass

through the DB0~DB3 lines. The RD line is the READ

clock input. Data in the RAM are clocked out on the fall-

ing edge of the RD signal, and the clocked out data will

then appear on the DB0~DB3 lines. It is recommended

that the host controller read correct data during the inter-

val between the rising edge and the next falling edge of

the RD signal. The WR line is the WRITE clock input. The

data, address, and command on the DB0~DB3 lines are

all clocked into the HT1647A on the rising edge of the

WR signal. There is an optional IRQ line to be used as an

interface between the host controller and the HT1647A.

The IRQ pin can be selected as a timer output or a WDT

overflow flag output by the S/W setting. The host con-

troller can perform the time base or the WDT function by

connecting with the IRQ pin of the HT1647A.