W25Q40BVZPIP datasheet(2/73 Pages) WINBOND

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W25Q40BV

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Table of Contents

GENERAL DESCRIPTION ............................................................................................................... 5

FEATURES....................................................................................................................................... 5

PIN CONFIGURATION SOIC 150 / 208-MIL ................................................................................... 6

PAD CONFIGURATION WSON 6X5-MM ........................................................................................ 6

PIN DESCRIPTION SOIC 150/208-MIL, AND WSON 6X5-MM ...................................................... 6

5.1

Package Types..................................................................................................................... 7

5.2

Chip Select (/CS).................................................................................................................. 7

5.3

Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 7

5.4

Write Protect (/WP)............................................................................................................... 7

5.5

HOLD (/HOLD) ..................................................................................................................... 7

5.6

Serial Clock (CLK)................................................................................................................ 7

BLOCK DIAGRAM............................................................................................................................ 8

FUNCTIONAL DESCRIPTION ......................................................................................................... 9

7.1

SPI OPERATIONS ............................................................................................................... 9

7.1.1

Standard SPI Instructions.......................................................................................................9

7.1.2

Dual SPI Instructions ..............................................................................................................9

7.1.3

Quad SPI Instructions.............................................................................................................9

7.1.4

Hold Function .........................................................................................................................9

7.2

WRITE PROTECTION ....................................................................................................... 10

7.2.1

Write Protect Features..........................................................................................................10

CONTROL AND STATUS REGISTERS ........................................................................................ 11

8.1

STATUS REGISTER .......................................................................................................... 11

8.1.1

BUSY....................................................................................................................................11

8.1.2

Write Enable Latch (WEL) ....................................................................................................11

8.1.3

Block Protect Bits (BP2, BP1, BP0)......................................................................................11

8.1.4

Top/Bottom Block Protect (TB).............................................................................................11

8.1.5

Sector/Block Protect (SEC) ..................................................................................................11

8.1.6

Complement Protect (CMP) .................................................................................................12

8.1.7

Status Register Protect (SRP1, SRP0).................................................................................12

8.1.8

Erase/Program Suspend Status (SUS) ................................................................................12

8.1.9

Security Register Lock Bits (LB3, LB2, LB1) ........................................................................12

8.1.10

Quad Enable (QE) ..............................................................................................................13

8.1.11

Status Register Memory Protection (CMP = 0)...................................................................14

8.1.12

Status Register Memory Protection (CMP = 1)...................................................................15

8.2

INSTRUCTIONS................................................................................................................. 16

8.2.1

Manufacturer and Device Identification ................................................................................16

8.2.2

Instruction Set Table 1 (Erase, Program Instructions) ..........................................................17

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