9ZX21201 datasheet(2/16 Pages) IDT

2 / 16 page

IDT®

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

1682B- 12/08/11

9ZX21201

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

Pin Configuration

Functionality at Power Up (PLL Mode)

100M_133M#

DIF_IN

(MHz)

DIF

100.00

DIF_IN

133.33

DIF_IN

PLL Operating Mode Readback Table

HiBW_BypM_LoBW#

Byte0, bit 7

Byte 0, bit 6

Low (Low BW)

Mid (Bypass)

High (High BW)

PLL Operating Mode

HiBW_BypM_LoBW#

MODE

Low

PLL Lo BW

Mid

Bypass

High

PLL Hi BW

NOTE: PLL is OFF in Bypass Mode

Tri-level Input Thresholds

Level

Voltage

Low

<0.8V

Mid

1.2<Vin<1.8V

High

Vin > 2.2V

MLF Power Connections

VDD

GND

Analog PLL

Analog Input

25,40,56

24,32,49,57

23,33,41,48,

DIF clocks

Pin Number

Description

SMB_A1_tri

SMB_A0_tri

9ZX21201 SMBus Addressing

SMBus Address

(Rd/Wrt bit = 0)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDDA 148 GND

GNDA 247 DIF_7#

IREF 346 DIF_7

100M_133M# 445 vOE7#

HIBW_BYPM_LOBW# 544 vOE6#

CKPWRGD_PD# 643 DIF_6#

GND 742 DIF_6

VDDR 841 GND

DIF_IN 940 VDD

DIF_IN# 10

39 DIF_5#

SMB_A0_tri 11

38 DIF_5

SMBDAT 12

37 vOE5#

SMBCLK 13

36 vOE4#

SMB_A1_tri 14

35 DIF_4#

DFB_OUT# 15

34 DIF_4

DFB_OUT 16

33 GND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Notes: Pins with ^ prefix have internal ~100K pullup

Pins with v prefix have internal ~100K pulldown.

9ZX21201

9ZX21201 Datasheet(PDF) 2 Page - Integrated Device Technology

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