MPC9230 datasheet(7/16 Pages) IDT

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MPC9230 REVISION 8 MARCH 29, 2010

MPC9230 Data Sheet

800MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER

Table 9. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40°C to +85°C)(1)

1. AC characteristics apply for parallel output termination of 50

Ω to VTT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fXTAL

Crystal Interface Frequency Range

MHz

fREF

FREF_EXT Reference Frequency Range

(fVCO,MAX÷M)·4(2)

2. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable PLL operation.

MHz

fVCO

VCO Frequency Range(3)

3. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ M ÷ 4.

800

1500

MHz

fMAX

Output Frequency

N = 11 (

÷1)

N = 00 (

÷2)

N = 01 (

÷4)

N = 10 (

÷8)

400

200

100

750.00

375.00

187.50

93.75

MHz

fS_CLOCK

Serial Interface Programming Clock Frequency(4)

4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock

in test mode 6. See APPLICATIONS INFORMATION for more details.

MHz

tP,MIN

Minimum Pulse Width

(S_LOAD, P_LOAD)

Output Duty Cycle

tr, tf

Output Rise/Fall Time

0.05

0.3

20% to 80%

Setup Time

S_DATA to S_CLOCK

S_CLOCK to S_LOAD

M, N to P_LOAD

Hold Time

S_DATA to S_CLOCK

M, N to P_LOAD

tJIT(CC)

Cycle-to-Cycle Jitter

N = 11 (

÷1)

N = 00 (

÷2)

N = 01 (

÷4)

N = 10 (

÷8)

130

160

tJIT(CC)

Period Jitter

N = 11 (

÷1)

N = 00 (

÷2)

N = 01 (

÷4)

N = 10 (

÷8)

120

140

tLOCK

Maximum PLL Lock Time

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