1645C—10/18/10

Advance Information

9DBL411B

Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI

5

Absolute Maximum Ratings

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Notes

Maximum Supply Voltage

VDDA

Core Supply Voltage

4.6

V

1,7

Maximum Supply Voltage

VDD_IO

Low-Voltage Differential I/O Supply

0.99

3.8

V

1,7

Maximum Input Voltage

V

IH

3.3V LVCMOS Inputs

4.6

V

1,7,8

Minimum Input Voltage

V

IL

Any Input

Vss - 0.5

V

1,7

TambCOM

Commercial Range

0

70

°C

1

TambIND

Industrial Range

-40

85

°C

1

Storage Temperature

Ts

-

-65

150

Input ESD protection

ESD prot

Human Body Model

2000

V

1,7

Ambient Operating Temp

Electrical Characteristics - Input/Supply/Common Output Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Notes

Supply Voltage

VDDxxx

Supply Voltage

3.000

3.600

V

1

Supply Voltage

VDDxxx_IO

Low-Voltage Differential I/O Supply

0.99

3.600

V

1

Input High Voltage

V

IHSE

Single-ended inputs

2

V

V

1

Input Low Voltage

V

ILSE

Single-ended inputs

V

0.8

V

1

Differential Input High Voltage

V

IHDIF

Differential inputs

(single-ended measurement)

600

1.15

V

1

Differential Input Low Voltage

V

ILDIF

Differential inputs

(single-ended measurement)

V

300

V

1

Input Slew Rate - DIF_IN

dv/dt

Measured differentially

0.4

8

V/ns

2

Input Leakage Current

I

IN

V

-5

5

uA

1

I

DD_3.3V

VDDA supply current

20

mA

1

I

DD_IO_133M

VDD_IO supply @ fOP = 133MHz

20

mA

1

I

DD_SB_3.3V

VDDA supply current, Input

stopped, OE# pins all high

750

uA

1

I

DD_SBIO

VDD_IO supply, Input stopped,

OE# pins all high

150

uA

1

Input Frequency

F

i

V

15

150

MHz

2

Pin Inductance

L

pin

7nH

1

C

IN

Logic Inputs

1.5

5

pF

1

C

OUT

Output pin capacitance

6

pF

1

OE# latency

(at least one OE# is low)

T

OE#LAT

Number of clocks to enable or

disable output from

assertion/deassertion of OE#

13

periods

1

Clock stabilization time (from all

OE# high to first OE# low).

T

STAB

Delay from assertion of first OE#

to first clock out (assumes input

clock running)

150

ns

1

Tdrive_OE#

T

DROE#

Output enable after

OE# de-assertion

10

ns

1

Tfall_OE#

T

FALL

5ns

1

Trise_OE#

T

RISE

5ns

1

Operating Supply Current

Power Down Current

(All OE# pins High)

Fall/rise time of OE# inputs

Input Capacitance