AD9628 datasheet(39/44 Pages) AD

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AD9628

Rev. 0 | Page 39 of 44

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Interfacing to High Speed ADCs via SPI.

Power Modes (Register 0x08)

Bits[7:6]—Open

Bit 5—External Power-Down Pin Function

If set, the external PDWN pin initiates power-down mode.

If clear, the external PDWN pin initiates standby mode.

Bits[4:2]—Open

Bits[1:0]—Internal Power-Down Mode

In normal operation (Bits[1:0] = 00), both ADC channels are

active.

In power-down mode (Bits[1:0] = 01), the digital data path clocks

are disabled while the digital data path is reset. Outputs are

disabled.

In standby mode (Bits[1:0] = 10), the digital data path clocks

and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), the digital data path clocks

are disabled while the digital data path is held in reset. The outputs

are enabled in this state. For optimum performance, it is recom-

mended that both ADC channels be reset simultaneously. This

is accomplished by ensuring that both channels are selected via

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other

low frequency noise, such as homodyne or direct-conversion

receivers, chopping in the first stage of the AD9628 is a feature

that can be enabled by setting Bit 2. In the frequency domain,

chopping translates offsets and other low frequency noise to

fCLK/2 where it can be filtered.

Bits[1:0]—Open

Output Mode (Register 0x14)

Bits[7:6]—Output Port Logic Type

00 = CMOS, 1.8 V

10 = LVDS, ANSI

11 = LVDS, reduced range

Bit 5—Output Interleave Enable

For LVDS outputs, setting Bit 5 enables interleaving. Channel A

is sent coincident with a high DCO clock, and Channel B is

coincident with a low DCO clock. Clearing Bit 5 disables the

interleaving feature. Channel A is sent on least significant bits

(LSBs), and Channel B is sent on most significant bits (MSBs).

The even bits are sent coincident with a high DCO clock, and

the odd bits are sent coincident with a low DCO clock.

For CMOS outputs, setting Bit 5 enables interleaving in CMOS

DDR mode. On ADC Output Port A, Channel A is sent coincident

with a low DCO clock, and Channel B is coincident with a high

DCO clock. On ADC Output Port B, Channel B is sent coincident

with a low DCO clock, and Channel A is coincident with a high

DCO clock. Clearing Bit 5 disables the interleaving feature, and

data is output in CMOS SDR mode. Channel A is sent to Port A,

and Channel B is sent to Port B.

Bit 4—Output Port Disable

Setting Bit 4 high disables the output port for the channels

selected in Bits[1:0] of the device index register (Register 0x05).

Bit 3—Open

Bit 2—Output Invert

Setting Bit 2 high inverts the output port data for the channels

selected in Bits[1:0] of the device index register (Register 0x05).

Bits[1:0]—Output Format

00 = offset binary

01 = twos complement

10 = Gray code

Sync Control (Register 0x3A)

Bits[7:3]—Open

Bit 2—Clock Divider Next Sync Only

If the clock divider sync enable bit (Address 0x3A, Bit 1) is high,

Bit 2 allows the clock divider to sync to the first sync pulse it

receives and to ignore the rest. The clock divider sync enable bit

resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high. This is continuous sync mode.

Bit 0—Open

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment they

are written. Setting Bit 0 of this transfer register high initializes

the settings in the ADC sample rate override register (Address

0x100).

Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device.

Any attempt to upgrade the default speed grade results in a chip

power-down. Settings in this register are not initialized until Bit 0

of the transfer register (Register 0xFF) is written high.

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