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HT95R22 Datasheet(PDF) 17 Page - Holtek Semiconductor Inc

Part # HT95R22
Description  I/O Type Phone 8-bit MCU
PDF  52 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT95R22 Datasheet(HTML) 17 Page - Holtek Semiconductor Inc

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HT95R22
Rev. 1.00
17
January 6, 2009
Timer/Event Counters
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The device contains two
count-up timers of 16-bit capacity. One of these timers
has three different operating modes, and can be config-
ured to operate as a general timer, an external event
counter or as a pulse width measurement device.
There are two types of registers related to the
Timer/Event Counters. The first are the registers that
contains the actual value of the Timer/Event Counter
and into which an initial value can be preloaded, and are
known as TMR0L/TMR0H and TMR1L/TMR1H. Read-
ing these register pairs retrieves the contents of the
Timer/Event Counters. The second type of associated
register are the Timer Control Registers, which defines
the timer options and determines how the Timer/Event
Counters are to be used, and have the name TMR0C
and TMR1C. Timer/Event Counter 0 can have its timer
clock configured to come from the internal clock source
or from an external timer pin.
Configuring the Timer/Event Counter Input Clock
Source
For Timer/Event Counter 0, the internal timer clock
source can originate from either the system clock/4 sys-
tem clock or from an external clock source. For
Timer/Event Counter 1, the internal timer clock source
originates from the 32768Hz system clock. The system
clock input timer source is used when the Timer/Event
Counters 1 is in the timer mode or for Timer/Event Coun-
ter 0, when also in the pulse width measurement mode.
An external clock source is used when the Timer/Event
Counter 0 is in the event counting mode, the clock
source being provided on the external timer pin TMR0.
Depending upon the condition of the T0E bit, each high
to low, or low to high transition on the external timer pin
will increment the counter by one.
Timer Registers
- TMR0L/TMR0H, TMR1L/TMR1H
The timer registers are special function register pairs
located in the Special Purpose Data Memory and is the
place where the 16-bit actual timer value is stored.
These register pairs are known as TMR0L/TMR0H and
TMR1L/TMR1H. The value in the timer register pair
increases by one each time an internal clock pulse is
received or an external transition occurs on the external
timer pin. The timer will count from the initial value
loaded by the preload register to the full count of FFFFH
at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then
be reset with the initial preload register value and
continue counting.
To achieve a maximum full range count of FFFFH the
preload register must first be cleared to all zeros. It
should be noted that after power-on, the preload register
will be in an unknown condition. Note that if the
Timer/Event Counter is switched off and data is written
to its preload register, this data will be immediately writ-
ten into the actual timer register. However, if the
Timer/Event Counter is enabled and counting, any new
data written into the preload data register during this pe-
1 6 - b i t
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
L o w B y t e B u f f e r
H i g h B y t e
L o w B y t e
1 6 - B i t T i m e r / E v e n t C o u n t e r
T M R 0
T 0 E
T i m e r / E v e n t C o u n t e r
M o d e C o n t r o l
T 0 O N
f S Y S / 4
T 0 M 1
T 0 M 0
16-bit Timer/Event Counter 0 Structure
1 6 - b i t
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
L o w B y t e B u f f e r
H i g h B y t e
L o w B y t e
1 6 - B i t T i m e r / E v e n t C o u n t e r
T i m e r / E v e n t C o u n t e r
M o d e C o n t r o l
T 1 O N
3 2 7 6 8 H z
T 1 M 1
T 1 M 0
16-bit Timer/Event Counter 1 Structure



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