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NP50P04SLG Datasheet(PDF) 2 Page - Renesas Technology Corp |
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NP50P04SLG Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 8 page  NP50P04SLG Chapter Title R07DS0241EJ0100 Rev.1.00 Page 2 of 6 Feb 09, 2011 Electrical Characteristics (TA = 25 °C) Item Symbol Min Typ Max Unit Test Conditions Zero Gate Voltage Drain Current IDSS −1 μA VDS = −40 V, VGS = 0 V Gate Leakage Current IGSS m10 μA VGS = m20 V, VDS = 0 V Gate to Source Threshold Voltage VGS(th) −1.0 −1.4 −2.5 V VDS = VGS, ID = −250 μA Forward Transfer Admittance ∗ 1 | yfs | 12 44 S VDS = −10 V, ID = −25 A RDS(on)1 8.2 9.6 m Ω VGS = −10 V, ID = −25 A Drain to Source On-state Resistance ∗ 1 RDS(on)2 9.8 15 m Ω VGS = −4.5 V, ID = −25 A Input Capacitance Ciss 3800 5700 pF VDS = −10 V, Output Capacitance Coss 740 1120 pF VGS = 0 V, Reverse Transfer Capacitance Crss 500 905 pF f = 1 MHz Turn-on Delay Time td(on) 11 24 ns Rise Time tr 15 39 ns VDD = −20 V, ID = −25 A, VGS = −10 V, Turn-off Delay Time td(off) 250 505 ns RG = 0 Ω Fall Time tf 150 380 ns Total Gate Charge QG 100 150 nC VDD = −32 V, Gate to Source Charge QGS 13 nC VGS = −10 V, Gate to Drain Charge QGD 30 nC ID = −50 A Body Diode Forward Voltage ∗ 1 VF(S-D) 0.96 1.5 V IF = −50 A, VGS = 0 V Reverse Recovery Time trr 50 ns IF = −50 A, VGS = 0 V, Reverse Recovery Charge Qrr 63 nC di/dt = −100 A/ μs Note: ∗1. Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2% TEST CIRCUIT 1 AVALANCHE CAPABILITY RG = 25 Ω 50 Ω L VDD VGS = −20 → 0 V BVDSS IAS ID VDS Starting Tch VDD D.U.T. TEST CIRCUIT 3 GATE CHARGE TEST CIRCUIT 2 SWITCHING TIME PG. RG 0 VGS(−) D.U.T. RL VDD τ = 1 s μ Duty Cycle ≤ 1% VGS Wave Form VDS Wave Form VGS(−) 10% 90% VGS 10% 0 VDS(−) 90% 90% td(on) tr td(off) tf 10% τ VDS 0 ton toff PG. PG. 50 Ω D.U.T. RL VDD IG = −2 mA − |
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