R5F2136CSDFP datasheet(41/61 Pages) RENESAS

41 / 61 page

R8C/36T-A Group

4. Electrical Characteristics

R01DS0055EJ0100 Rev.1.00

Page 41 of 58

Dec 09, 2011

Note:

1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.

Figure 4.3

Power-on Reset Circuit Characteristics

Notes:

1. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in

UART mode.

2. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator.

Table 4.10

Power-On Reset Circuit Characteristics (1)

(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr =

20°C to 85°C (N version)/

40°C to 85°C (D version))

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

trth

External power VCC rise gradient

―

50,000

mV/msec

Table 4.11

High-Speed On-Chip Oscillator Circuit Characteristics

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

―

High-speed on-chip oscillator frequency

after reset

Vcc = 1.8 V to 5.5 V,

20°C  Topr  85°C

(N version)

40°C  Topr  85°C

(D version)

―

MHz

High-speed on-chip oscillator frequency

when 01b or 10b is written to bits

FRA25 and FRA24 in the FRA2 register

(1)

—

36.864

—

MHz

High-speed on-chip oscillator frequency

when 10b is written to bits FRA25 and

FRA24 in the FRA2 register

—32—

MHz

High-speed on-chip oscillator frequency

dependence on temperature and power

supply voltage (2)

 1.5

―

1.5

―

Oscillation stability time

Vcc = 5.0 V, Topr = 25°C

―

250

―μs

―

Self power consumption at oscillation

Vcc = 5.0 V, Topr = 25°C

―

500

―μA

Notes:

1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to the Voltage Detection

Circuit chapter of User’s Manual: Hardware for details.

2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable

a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain

tw(por) for 1 ms or more.

Vdet0

(1)

0.5 V

Internal

reset signal

tw(por)

(2)

Voltage detection 0

circuit response time

Vdet0

(1)

fOCO-S

 32

fOCO-S

 32

External

Power VCC

trth

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