SAB80C166 datasheet(42/52 Pages) SIEMENS

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SAB 80C166/83C166

Semiconductor Group

AC Characteristics (cont’d)

Demultiplexed Bus

CC = 5 V ± 10 %;

SS = 0 V

A = 0 to +70 ˚C

for SAB 83C166-5M, SAB 80C166-M

A = -40 to +85 ˚C

for SAB 83C166-5M-T3, SAB 80C166-M-T3

L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

ALE cycle time = 4 TCL + 2

A + tC + tF (100 ns at 20-MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

CC 15 +

–

TCL - 10 +

–ns

Address setup to ALE

CC 10 +

–

TCL - 15 +

–ns

ALE falling edge to RD,

WR (with RW-delay)

CC 15 +

–

TCL - 10

–ns

ALE falling edge to RD,

WR (no RW-delay)

CC -10 +

–

-10

–ns

RD, WR low time

(with RW-delay)

CC 40 +

–

2TCL - 10

–ns

RD, WR low time

(no RW-delay)

CC 65 +

–

3TCL - 10

–ns

RD to valid data in

(with RW-delay)

SR –

30 +

–

2TCL - 20

RD to valid data in

(no RW-delay)

SR –

55 +

–

3TCL - 20

ALE low to valid data in

SR –

A + tC

–

3TCL - 20

A + tC

Address to valid data in

SR –

+ 2

A + tC

–

4TCL - 25

+ 2

A + tC

Data hold after RD

rising edge

SR 0

–

0–ns

Data float after RD rising

edge (with RW-delay)

SR –

35 +

–

2TCL - 15

Data float after RD rising

edge (no RW-delay)

SR –

15 +

–

TCL - 10

Data valid to WR

CC 35 +

–

2TCL - 15

–ns

Data hold after WR

CC 15 +

–

TCL - 10 +

–ns

SAB80C166 Datasheet(PDF) 42 Page - Siemens Semiconductor Group

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