ADP7102ACPZ-9.0-R7 datasheet(25/28 Pages) AD

25 / 28 page

Data Sheet

ADP7102

Rev. A | Page 25 of 28

OUTLINE DIMENSIONS

PIN 1

INDICATOR

(R 0.2)

EXPOSED

PAD

BOTTOM VIEW

TOP VIEW

INDEX

AREA

3.00

BSC SQ

SEATING

PLANE

0.80

0.75

0.70

0.30

0.25

0.18

0.05 MAX

0.02 NOM

0.80 MAX

0.55 NOM

0.20 REF

0.50 BSC

COPLANARITY

0.08

2.48

2.38

2.23

1.74

1.64

1.49

0.50

0.40

0.30

COMPLIANT

TO JEDEC STANDARDS MO-229-WEED-4

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-5)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-012-A A

1.27

0.40

1.75

1.35

2.41

0.356

0.457

4.00

3.90

3.80

6.20

6.00

5.80

5.00

4.90

4.80

0.10 MAX

0.05 NOM

3.81 REF

0.25

0.17

8°

0°

0.50

0.25

45°

COPLANARITY

0.10

1.04 REF

1.27 BSC

SEATING

PLANE

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

BOTTOM VIEW

TOP VIEW

0.51

0.31

1.65

1.25

3.098

Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters

ADP7102ACPZ-9.0-R7 Datasheet(PDF) 25 Page - Analog Devices

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