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HMC984LP4E

v02.0112

DIGITAL PHASE-FREQUENCY DETECTOR

The HMC984LP4E has two outputs, UPSAT and DNSAT, which indicate to the HMC983LP5E whether the Reference

or the VCO is leading in phase. These outputs are CMOS signal with DVDD levels. When HMC983LP5E detects

saturation (large phase error), it configures itself, and the HMC984LP4E in order to eliminate or reduce cycle clipping.

There are additional controls for adjusting the CSP operation in HMC983LP5E. The controls for CSP feature are;

1.

Register 0Eh bits [18:15] control the step size, where step is a VCO cycle.

2.

Register 0Eh bit [29] increases the step size by a factor of 16 for operations with low reference frequencies.

The actual operation of CSP will depend on the Reference and VCO frequencies and will need to be tailored for each

application.

Charge Pump

The charge pump in HMC984LP4E converts the phase detector digital outputs to appropriate current level that is

proportional to phase difference between the reference and the VCO. A simplified block diagram of the charge pump

is shown in Figure 25. The HMC984LP4E CP has programmable current gain and offset current.

Charge Pump Gain Current

CP gain current defines the gain of Phase Detector vs. Phase Difference in Amps/radians. The UP and DOWN

gain currents are configured in Reg 04h[6:0] and Reg 04h[13:7] respectively. Both UP and DOWN currents can be

programmed to provide up to 2.5 mA independently in 127 steps (20 μA/step). Resulting phase detector gain is the

total current from one side divided by 2π. For example, if both UP and DOWN currents are set 2 mA each, the gain

would be 2 mA/2π = 318.31 μA/radian. Typically both of the gain currents are set to the same value.

Charge Pump Phase Offset

Either of the UP or DOWN charge pumps may have a DC offset current added to it. Offset current allows the phase

detector to operate with a phase offset between the reference and the divided VCO inputs. The phase offset is

proportional to the ratio of the offset current to the main current times the period of the phase comparison clock.

Offset Current

1

PD Phase offset=

CP Current

PD

f

×

(Eq 5)

It is recommended to operate the HMC984LP4E with a phase offset when using fractional mode to reduce non-linear

effects from any UP and DN pump mismatches that may exist. Phase noise in fractional mode is strongly affected by

charge pump offset.

The magnitude of offset current is set in Reg 04h[20:14], and can be added to the UP (Reg 04h[21] = 1) or DOWN (Reg

04h[22] = 1) pumps.

As an example, if the main pump gain was set at 2 mA, an offset of 160 µA (Reg 04h[20:14] = 20h) and 50 MHz PFD

rate would represent a phase offset of about (160/2000)*360 = 28.8 degrees or (163.5 μA/2000 μA)*20 ns = 1.6 ns

phase offset at the PD input.

Charge Pump High Gain (HiK) Mode

Operating the CP of the HMC984LP4E in High Gain mode (Reg 04h[23] = 1) can improve PLL phase noise performance

by up to 3 dB. In High Gain mode the charge pump can deliver current of 3.5 mA + normal programmed CP current.

High gain mode can be used without the normal charge pump current in which case the loop filter should be designed

with a current of 3.5 mA. In the case where high gain mode is used with the normal CP current, the loop filter should be

designed with a charge pump current of 3.5 mA + programmed CP current. The high gain mode current is depended

on the loop filter voltage, therefore the high gain mode should be used with active loop filters to keep a constant

voltage a the charge pump output.