DM9620EP datasheet(19/71 Pages) DAVICOM

19 / 71 page

DM9620/DM9620I

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9620/DM9620I -15-DS-P02

December 26, 2011

4.5 RX Status Register ( 06H )

Bit

Name

Default

Description

PHS0,RO

Runt Frame

It is set to indicate the received frame has the size smaller than 64 bytes.

PHS0,RO

Multicast Frame

It is set to indicate the received frame has a multicast address.

LCS

PHS0,RO

Late Collision Seen

It is set to indicate a late collision found during the frame reception.

RWTO

PHS0,RO

Receive Watchdog Time-Out

It is set to indicate receive more than 2048 bytes.

PLE

PHS0,RO

Physical Layer Error

It is set to indicate a physical layer error found during the frame reception.

PHS0,RO

Alignment Error

It is set to indicate the received frame ends with a non-byte boundary.

PHS0,RO

CRC Error

It is set to indicate the received frame ends with a CRC error.

FOE

PHS0,RO

FIFO Overflow Error

It is set to indicate a FIFO Overflow error happens during the frame reception.

4.6 Receive Overflow Counter Register ( 07H )

This register can be cleared by writing any data this byte. Or they also can be cleared by read this byte if register 0H bit 5 is 0”.

Bit

Name

Default

Description

RXFU

PHS0,RW

Receive Overflow Counter Overflow

This bit is set when the ROC has an overflow condition.

6:0

ROC

PHS0,RW

Receive Overflow Counter

This is a statistic counter to indicate the received packet count upon FIFO

overflow.

DM9620EP Datasheet(PDF) 19 Page - Davicom Semiconductor, Inc.

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