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LTM9002 Datasheet(PDF) 23 Page - Linear Technology |
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LTM9002 Datasheet(HTML) 23 Page - Linear Technology |
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23 / 32 page ![]() LTC2159 23 2159f Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serialinterfacethatprogramtheA/Dmodecontrolregisters. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be writ- ten to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers shouldbeprogrammedassoonaspossibleafterthepower supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset SPI write command is complete, bit D7 is automatically set back to zero. applicaTions inForMaTion Table 3. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X Bits 7 RESET Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers are reset to 00h. The ADC is momentarily placed in sleep mode. This bit is automatically set back to zero at the end of the SPI write command. The Reset register is write-only. Data read back from the reset register will be random. Bits 6-0 Unused, Don’t Care Bits REGISTER A1: POWER DOWN REGISTER (ADDRESS 01h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X PWROFF1 PWROFF0 Bits 7-2 Unused, Don’t Care Bits Bits 1-0 PWROFF1: PWROFF0 Power Down Control Bits 00 = Normal Operation 01 = Not Used 10 = Nap Mode 11 = Sleep Mode |
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