LTC3829 datasheet(45/54 Pages) LINER

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LTC3838

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from cycle to cycle in a well designed, low noise PCB

implementation. Variation in the phase of SW node pulse

can suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompensa-

tion of the loop can be used to tame a poor PCB layout if

regulator bandwidth optimization is not required.

Pay special attention to the region of operation when one

controller channel is turning on (right after its current

comparator trip point) while the other channel is turning

off its top MOSFET at the end of its on-time. This may

cause minor phase-lock jitter at either channel due to

noise coupling.

Reduce VIN from its nominal level to verify operation of

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering VIN while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins.

APPLICATIONS INFORMATION

The capacitor placed across the current sensing pins needs

to be placed immediately adjacent to the pins of the IC.

This capacitor helps to minimize the effects of differential

noise injection due to high frequency capacitive coupling.

If problems are encountered with high current output

loading at lower input voltages, look for inductive coupling

between CIN, top and bottom MOSFET components to the

sensitive current and voltage sensing traces.

In addition, investigate common ground path voltage pickup

between these components and the SGND pin of the IC.

High Switching Frequency Operation

At high switching frequencies there may be an increased

sensitivity to noise. Special care may need to be taken to

prevent cycle-by-cycle instability and/or phase-lock jitter.

First, carefully follow the recommended layout techniques

to reduce coupling from the high switching voltage/current

traces. Additionally, use low ESR and low impedance X5R

or X7R ceramic input capacitors: up to 5μF per Ampere of

load current may be needed. If necessary, increase ripple

sense voltage by increasing sense resistance value and

VRNG setting, to improve noise immunity.

LTC3829 Datasheet(PDF) 45 Page - Linear Technology

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