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LTC4211

4211fb

OPERATION

a start-up check to make sure the supply voltage is above

its 2.3V UVLO threshold (see Time Point 1). If the input

supply voltage is valid, the gate of the external pass tran-

sistor is pulled to ground by the internal 200μA current

source connected at the GATE pin. The TIMER pin is held

low by an internal N-channel pull-down transistor (see

M6, LTC4211 Block Diagram) and the FILTER pin voltage

is pulled to ground by an internal 10μA current source.

Once VCC and ON (the ON pin is >1.316) are valid, the

LTC4211 checks to make sure that GATE is OFF (VGATE <

0.2V) at Time Point 2. An internal timing circuit is enabled

and the TIMER pin voltage ramps up at the rate described by

Equation 1. At Time Point 3 (the timing period programmed

by CTIMER), the TIMER pin voltage equals VTMR (1.236V).

Next, the TIMER pin voltage ramps down to Time Point 4

where the LTC4211 performs two checks: (1) FILTER pin

voltage is low (VFILTER < 1.156V) and (2) FAULT pin volt-

age is high (VFAULT > 1.286V). If both conditions are met,

the LTC4211 begins a second timing (soft-start) cycle.

Second Timing (Soft-Start) Cycle

At the beginning of the second timing cycle (Time Point 5),

the LTC4211’s FAST COMP is armed and an internal 10μA

current source working with an internal charge pump

provides the gate drive to the external pass transistor. The

LTC4211 automatically limits the inrush current in one of

two ways: by controlling the GATE pin voltage slew rate

or by actively limiting the inrush current. If GATE voltage

slew rate control is preferred, an external capacitor CGATE

can be used from GATE to ground, as shown in Figure 6.

An expression for the GATE voltage slew rate is given by

Equation 3:

VGATE Slew Rate,

dVGATE

10µA

CGATE

(3)

Adding CGATE slows the GATE voltage slew rate at the ex-

pense of slower system turn-on and turn-off time. Should

this technique be used, values for CGATE less than 150nF

are recommended.

The inrush current being delivered to the load while

the GATE is ramping is dependent on CLOAD and CGATE.

Equation 4 gives an expression for the inrush current

during the second timing cycle:

IINRUSH =

dVGATE

•CLOAD = 10µA •

CLOAD

CGATE

(4)

For example, if CGATE = 3300pF and CLOAD = 2000μF, the

inrush current charging CLOAD is:

IINRUSH = 10µA •

2000µF

0.0033µF

= 6.06A

(5)

At Time Point 6, the output voltage trips COMP2’s thresh-

old, signaling an output voltage “power good” condition.

At Time Point 7, RESET is asserted high, SLOW COMP is

armed and the LTC4211 enters a fault monitor mode. The

TIMER voltage then ramps down to Time Point 8.

Power-Off Cycle

As shown at Time Point 9, an external hard reset is initiated

by pulling the ON pin low (VON < 1.236V). The GATE pin

voltage is ramped to ground by the internal 200μA cur-

rent source, discharging CGATE and turning off the pass

transistor. As CLOADdischarges,theoutputvoltagecrosses

COMP2’s threshold, signaling a “power bad” condition at

Time Point 10. At this point, RESET is asserted low.

Figure 6. Using an External Capacitor at GATE for

GATE Voltage Slew Rate Control

Si4410DY

RSENSE

0.007Ω

CGATE*

CLOAD

4211 F06

VCC

SENSE

LTC4211**

GATE

36k

VOUT

VIN

15k

VALUES ≤150nF SUGGESTED

ADDITIONAL DETAILS OMITTED

FOR CLARITY

dVGATE

VGATE SLEW RATE CONTROL

10μA

CGATE

()

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