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MMA5124KW Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc

Part # MMA5124KW
Description  PSI5 Inertial Sensor
PDF  55 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MMA5124KW Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc

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Sensors
Freescale Semiconductor, Inc.
13
MMA51xxKW
3.1.2
Factory Configuration Register (DEVCFG1)
The factory configuration register is a factory programmed, read only register which contains user specific device configuration
information. The factory configuration register is included in the factory programmed OTP CRC verification.
3.1.2.1
Range Indication Bits (RNG[2:0])
The range indication bits are factory programmed and indicate the full-scale range of the device as shown below.
3.1.3
Device Configuration 2 Register (DEVCFG2)
Device configuration register 2 is a user programmable OTP register that contains device configuration information.
3.1.3.1
User Configuration Lock Bit (LOCK_U)
The LOCK_U bit allows the user to prevent writes to the user configuration array once programming is completed.
If the LOCK_U bit is written to ‘1’ when a PSI5 “Execute Programming of NVM” command is executed, the LOCK_U OTP bit
will be programmed. Upon completion of the OTP programming, an OTP readout will be executed, locking the array from future
OTP writes. The User Programmable OTP Array CRC Verification is also activated (Reference Section 3.2.2).
3.1.3.2
PCM Enable Bit (PCM)
The PCM bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code
Modulated signal proportional to the acceleration response. Reference Section 3.5.3.7 for more information regarding the PCM
output. When the PCM bit is cleared, the PCM output pin is actively pulled low.
Location
Bit
Address
Register
7
6543210
$04
DEVCFG1
0
0101
RNG[2]
RNG[1]
RNG[0]
Factory Default
0
0100000
RNG[2]
RNG[1]
RNG[0]
Full-Scale Acceleration
Range
g-Cell Design
PSI5 Init Data
Transmission (D9)
Reference Table 12
0
0
0
Reserved
N/A
0001
0
0
1
±60g
Medium-g
0111
0
1
0
Reserved
N/A
0010
0
1
1
±120g
Medium-g
1000
1
0
0
Reserved
N/A
0011
1
0
1
±240g
High-g
1001
1
1
0
Reserved
N/A
0100
1
1
1
±480g
High-g
1010
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$05
DEVCFG2
LOCK_U
PCM
SYNC_PD
LATENCY
DATASIZE
BLANKTIME
P_CRC
BAUD
Factory Default
000
00000
PCM
PCM Output
0
Actively Pulled Low
1
PCM Signal Enabled



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