MMA6525KW datasheet(21/56 Pages) FREESCALE

21 / 56 page

Sensor

Freescale Semiconductor, Inc.

MMA65xx

3.1.12

Count Register (COUNT)

The count register is a read-only register which provides the current value of a free-running 8-bit counter derived from the pri-

mary oscillator. A 10-bit pre-scaler divides the primary oscillator frequency by 1024. Thus, the value in the register increases by

one count every 128

μs and the counter rolls over every 32.768 ms.

3.1.13

Offset Correction Value Registers (OFFCORR_X, OFFCORR_Y)

The offset correction value registers are read-only registers which contain the most recent offset correction increment / dec-

rement value from the offset cancellation circuit. The values stored in these registers indicate the amount of offset correction be-

ing applied to the SPI output data. The values have a resolution of 1 LSB.

3.1.14

Reserved Registers (Reserved)

Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and

performance.

3.2

Customer Accessible Data Array CRC Verification

3.2.1

OTP Shadow Register Array CRC Verification

The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of

g(x) = X3 + X + 1, with a seed value = ‘111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register.

3.2.2

Writable Register CRC Verification

The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when

the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X3+X+1, with a seed

value = ‘111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register.

Table 23. Count Register

Location

Bit

Address

7654

3210

$15

COUNT

COUNT[7]

COUNT[6]

COUNT[5]

COUNT[4]

COUNT[3]

COUNT[2]

COUNT[1]

COUNT[0]

Reset Value

0000

Table 24. Offset Correction Value Register

Location

Bit

Address

7654

3210

$16

OFFCORR_

X[7]

OFFCORR_

X[6]

OFFCORR_

X[5]

OFFCORR_

X[4]

OFFCORR_

X[3]

OFFCORR_

X[2]

OFFCORR_

X[1]

OFFCORR_

X[0]

$17

OFFCORR_

Y[7]

OFFCORR_

Y[6]

OFFCORR_

Y[5]

OFFCORR_

Y[4]

OFFCORR_

Y[3]

OFFCORR_

Y[2]

OFFCORR_

Y[1]

OFFCORR_

Y[0]

Reset Value

0000

Table 25. Reserved Registers

Location

Bit

Address

7654

3210

$1C

Reserved

$1D

Reserved

Reset Value

0000

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