MPC8379E datasheet(99/117 Pages) FREESCALE

99 / 117 page

MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This table provides the operating frequencies for the TePBGA II package under recommended operating

conditions (see Table 3).

22.1

System PLL Configuration

The system PLL is controlled by the RCWLR[SPMF] parameter. The system PLL VCO frequency

depends on RCWLR[DDRCM] and RCWLR[LBCM]. Table 72 shows the multiplication factor encodings

for the system PLL.

NOTE

If RCWLR[DDRCM] and RCWLR[LBCM] are both cleared, the system

PLL VCO frequency = (CSB frequency)

× (System PLL VCO Divider).

If either RCWLR[DDRCM] or RCWLR[LBCM] are set, the system PLL

VCO frequency = 2

× (CSB frequency) × (System PLL VCO Divider).

The VCO divider needs to be set properly so that the System PLL VCO

frequency is in the range of 400–800 MHz.

Table 71. Operating Frequencies for TePBGA II

Parameter1

Minimum Operating

Frequency (MHz)

Maximum Operating

Frequency (MHz)

e300 core frequency (

core_clk)

333

800

Coherent system bus frequency (

csb_clk)

133

400

DDR2 memory bus frequency (MCK)1

250

400

DDR1 memory bus frequency (MCK) 2

167

333

Local bus frequency (LCLK

n)1

—

133

Local bus controller frequency (

lbc_clk)

—

400

PCI input frequency (CLKIN or PCI_CLK)

eTSEC frequency

133

400

Security encryption controller frequency

—

200

USB controller frequency

—

200

eSDHC controller frequency

—

200

SATA controller frequency

—

200

Notes:

1. The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting

csb_clk,

MCK, LCLK[0:2], and

core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.

The value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core,

USB modules, SATA, and eSDHC will not exceed their respective value listed in this table.

2. The DDR data rate is 2

× the DDR memory bus frequency.

3. The local bus frequency is ½, ¼, or 1/8 of the

lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×

the

csb_clk frequency (depending on RCWLR[LBCM]).

MPC8379E Datasheet(PDF) 99 Page - Freescale Semiconductor, Inc

MPC8379E Datasheet(HTML) 99 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL