MAG3110 datasheet(8/28 Pages) FREESCALE

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Freescale Semiconductor, Inc.

Figure 5. I2C Slave Timing Diagram

2.5

I2C Pullup Resistor Selection

The SCL and SDA signals are driven by open-drain buffers and a pullup resistor is required to make the signals rise to the high

state. The value of the pullup resistors depends on the system I2C clock rate and the capacitance load on the I2C bus.

Higher resistance value pullup resistors consume less power, but have a slower the rise time (due to the RC time constant

between the bus capacitance and the pullup resistor) and will limit the I2C clock frequency.

Lower resistance value pullup resistors consume more power, but enable higher I2C clock operating frequencies.

High bus capacitance is due to long bus lines or a high number of I2C devices connected to the bus. A lower value resistance

pullup resistor is required in higher bus capacitance systems.

For standard 100 kHz clock I2C, pullup resistors typically are between 5k and 10 k

Ω. For a heavily loaded bus, the pullup resistor

value may need to be reduced. For higher speed 400 kHz or 800 kHz clock I2C, bus capacitance will need to be kept low, in

addition to selecting a lower value resistance pullup resistor. Pullup resistors for high speed buses typically are about 1 K

Ω.

In a well designed system with a microprocessor and one I2C device on the bus, with good board layout and routing, the I2C bus

capacitance can be kept under 20 pF. With a 1K pullup resistor, the I2C clock rates can be well in excess of a few megahertz.

MAG3110 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc