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CY29946AXC Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY29946AXC
Description  2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer
PDF  9 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY29946AXC Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY29946
Document #: 38-07286 Rev. *G
Page 4 of 9
AC Electrical Specifications
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range[5]
Parameter
Description
Conditions
Min
Typ
Max
Unit
Fmax
Input Frequency[6]
VDD = 3.3 V
–
–
200
MHz
VDD = 2.5 V
–
–
170
Tpd
TTL_CLK To Q Delay[6]
5.0
–
11.5
ns
FoutDC
Output Duty Cycle[6, 7]
Measured at VDD/2
45–55
%
tpZL, tpZH
Output enable time (all outputs)
2
–
10
ns
tpLZ, tpHZ
Output disable time (all outputs)
2
–
10
ns
Tskew
Output-to-Output Skew[6, 8]
–
150
250
ps
Tskew(pp)
Part-to-Part Skew[9]
–2.0
4.5
ns
Tr/Tf
Output Clocks Rise/Fall Time[8] 0.8 V to 2.0 V, VDD = 3.3 V
0.10
–
1.0
ns
0.6 V to 1.8 V, VDD = 2.5 V
0.10
–
1.3
Notes
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50
 transmission lines.
7. 50% input duty cycle.
8. See Figure 1 on page 5.
9. Part-to-Part skew at a given temperature and voltage.
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