ADS5294IPFPR datasheet(26/67 Pages) TI1

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D15

D14

D13

D12

D11

D10

SDATA

SCLK

CSZ

SLOADS

SLOADH

SCLK

DSU

RESET

ADS5294

SLAS776B – NOVEMBER 2011 – REVISED JULY 2012

www.ti.com

SERIAL INTERFACE

ADS5294 has a set of internal registers that can be accessed by the serial interface formed by pins CSZ (Serial

interface Enable – Active Low), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).

When CSZ is low,

•

Serial shift of bits into the device is enabled.

•

Serial data (SDATA) is latched at every rising edge of SCLK.

•

SDATA is loaded into the register at every 24th SCLK rising edge

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CSZ pulse. The first eight bits form the register address and the remaining 16

bits the register data. The interface can work with SCLK frequencies from 15 MHz down to very low speeds (few

Hertz) and also with non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to the respective default values. Initialization can be done

in one of two ways:

1. Through a hardware reset, by applying a high pulse on the RESET pin; or

2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the

internal registers to the respective default values and then self-resets the bit low. In this case, the RESET pin

stays low (inactive).

Figure 44. Serial Interface Timing

SERIAL INTERFACE TIMING CHARACTERISTICS

Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V,

LVDD = 1.8 V, unless otherwise noted.

PARAMETER

MIN

TYP

MAX

UNIT

fSCLK

SCLK frequency (= 1/ tSCLK)

> DC

MHz

tSLOADS

CS to SCLK setup time

tSLOADH

SCLK to CS hold time

tDS

SDATA setup time

tDH

SDATA hold time

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