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LD49150PU10R Datasheet(PDF) 5 Page - STMicroelectronics |
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LD49150PU10R Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 22 page ![]() LD49150XX08, LD49150XX10, LD49150XX12 Pin configuration Doc ID 13446 Rev 3 5/22 3 Pin configuration Figure 5. Pin connections (top view for PPAK, bottom view for DFN) PPAK DFN6 (3 x 3 mm) Table 2. Pin description Pin n° for PPAK Pin n° for DFN Symbol Note 12 EN For fixed versions: Enable (Input) - Logic High = Enable, Logic Low = Shutdown. ADJ For adjustable versions: Adjustable regulator feedback input. Connect to resistor voltage divider. 23 VIN Input voltage which supplies current to the output power device. 3 1 GND Ground (TAB is connected to ground). 44 VOUT Regulator output. 56 VBIAS Input bias voltage for powering all circuitry on the regulator with the exception of the output power device. 5 N.C. Not connect. |
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