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CLVTH16373IZQLREP Datasheet(PDF) 2 Page - Texas Instruments |
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CLVTH16373IZQLREP Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 12 page ![]() SN74LVTH16373EP 3.3V ABT 16BIT TRANSPARENT DTYPE LATCH WITH 3STATE OUTPUTS SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. terminal assignments 123456 A 1OE NC NC NC NC 1LE B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2LE NC − No internal connection ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP − DL Tape and reel CLVTH16373IDLREP LH16373EP TSSOP − DGG Tape and reel CLVTH16373IDGGREP LH16373EP −40 °C to 85°C VFBGA − GQL CLVTH16373IGQLREP −40 C to 85 C VFBGA − ZQL (Pb-free) Tape and reel CLVTH16373IZQLREP LL373EP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. GQL OR ZQL PACKAGE (TOP VIEW) A B C D E F G H J K 1 2345 6 |
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