SN74LVTH16501EP

3.3V ABT 18BIT UNIVERSAL BUS TRANSCEIVER

WITH 3STATE OUTPUTS

SCBS784 − NOVEMBER 2003

2

POST OFFICE BOX 655303

description/ordering information (continued)

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

TSSOP − DGG

Tape and reel

CLVTH16501IDGGREP

LH16501EP

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when

LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is

low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the

outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are

complementary (OEAB is active high and OEBA is active low).

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by

the current-sinking/current-sourcing capability of the driver.

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

FUNCTION TABLE†

INPUTS

OUTPUT

OEAB

LEAB

CLKAB

A

OUTPUT

B

L

X

X

X

Z

H

HX

L

L

H

HX

H

H

H

L

↑

LL

H

L

↑

HH

H

LH

X

B0‡

H

L

L

X

B0§

† A-to-B data flow is shown; B-to-A flow is similar, but

uses OEBA, LEBA, and CLKBA.

‡ Output level before the indicated steady-state input

conditions were established, provided that CLKAB

was high before LEAB went low

§ Output level before the indicated steady-state input

conditions were established