SN8A1702A datasheet(22/145 Pages) SONIX

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 22

Revision 1.94

PIN DESCRIPTIONS

PIN NAME

TYPE

DESCRIPTION

VDD, VSS

Power supply input pins for digital circuit.

AVDD, AVSS

Power supply input pins for analog circuit.

VPP/VDD

OTP ROM programming pin. Connect to VDD in normal operation.

RST

System reset input pin. Schmitt trigger structure, active “low”, normal stay to “high”.

XIN, XOUT

I, O

External oscillator pins. RC mode from XIN.

P0.0 / INT0

Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resisters.

P0.1 / INT1

Port 0.1 and shared with INT1 trigger pin (Schmitt trigger) / Built-in pull-up resisters.

P0.2 / INT2

Port 0.2 and shared with INT2 trigger pin (Schmitt trigger) / Built-in pull-up resisters.

P1.0 ~ P1.5

I/O

Port 1.0~Port 1.5 bi-direction pins / Built-in pull-up resisters.

P2.0 ~ P2.7

I/O

Port 2.0~Port 2.7 bi-direction pins / Built-in pull-up resisters.

P4.0 ~ P4.7

I/O

Port 4.0~Port 4.7 bi-direction pins / Built-in pull-up resisters.

P5.0 / SCK

I/O

Port 5.0 bi-direction pin and SIO’s clock input/output / Built-in pull-up resisters.

P5.1 / SI

I/O

Port 5.1 bi-direction pin and SIO’s data input / Built-in pull-up resisters.

P5.2 / SO

I/O

Port 5.2 bi-direction pin and SIO’s data output / Built-in pull-up resisters.

P5.3 / BZ1 / PWM1

I/O

Port 5.3 bi-direction pin, TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin.

Built-in pull-up resisters.

P5.4 / BZ0 / PWM0

I/O

Port 5.4 bi-direction pin, TC0 ÷ 2 signal output pin for buzzer or PWM0 output pin.

Built-in pull-up resisters.

P5.5 ~ P5.7

I/O

Port 5.5~Port 5.7 bi-direction pins / Built-in pull-up resisters.

AVREFH

A/D converter high analog reference voltage.

AIN0 ~ AIN7

Analog signal input pins for ADC converter.

DAO

5-bit DAC signal output pin.

Table 1-4. SN8P1700 Pin Description

PIN CIRCUIT DIAGRAMS

Figure 1-2. Pin Circuit Diagram

Note: All of the latch output circuits are push-pull structures.

Port0 structure

PUR

Int. bus

PUR

PnM

Int. bus

PnM

Latch

Port1, 2, 4, 5 structure

PnM

Port0 structure

PUR

Int. bus

PUR

PnM

Int. bus

PnM

Latch

Port1, 2, 4, 5 structure

PnM

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