Endpoints

Internal Regulator

Clock and Reset

DAC

ADC

Microphone Bias

PCM2912A

The PCM2912A has the following three endpoints:

• Control endpoint (EP #0)

• Isochronous out audio data stream endpoint (EP #1)

• Isochronous in audio data stream endpoint (EP #2)

The control endpoint is the default endpoint. The control endpoint controls all functions of the PCM2912A by the

standard USB request and USB audio class-specific request from the host. The isochronous out audio data

stream endpoint is an audio sink endpoint, which receives the PCM audio data. The isochronous out audio data

stream endpoint accepts the asynchronous transfer mode. The isochronous in audio data stream endpoint is an

audio source endpoint, which transmits the PCM audio data. The isochronous in audio data stream endpoint

uses synchronous transfer mode.

All required power sources are generated by five internal regulators.

ground return pin (as described in Table 6); this pair must be decoupled with an appropriate capacitor. Note that

this capacitance affects inrush-current limitation. One band-gap reference circuit supplies reference voltage for all

regulators. BGND (pin 1) is provided for reference ground of the band-gap reference.

Table 6. Internal Regulator Summary

SUPPLIED CIRCUIT

OUTPUT

RETURN

Digital

DGND (pin 6)

Analog

AGND (pin 13)

Headphone (L-ch)

HGND (pin 20)

Headphone (R-ch)

HGND (pin 20)

PLL

PGND (pin 25)

The PCM2912A requires a 6-MHz (±500 ppm) clock for USB function and audio function, which can be

generated from a built-in crystal oscillator with a 6-MHz crystal resonator. The 6-MHz crystal resonator must be

connected to XTI (pin 8) and XTO (pin 7) with one high (1-M

Ω) resistor and two small capacitors, whose

capacitance depends on the load capacitance of the crystal resonator. An external clock can be supplied through

XTI; if an external clock is supplied, XTO must be left open. Because there is no clock disabling signal, using the

external clock supply is not recommended. SSPND (pin 29) is unable to use clock disabling.

V, typical (2.2 V to 2.7 V), and approximately 700

µs is required until the internal reset is released.

(pin 22) provide 13 mW at 32

amplifier and the PGA, which has +30 dB to –12 dB in 1-dB steps.

output with appropriate output impedance for electret-microphone driving. This output, MBIAS (pin 17), should be

bypassed to AGND (pin 13) through an appropriate capacitor to reduce the output noise level.

Copyright © 2008, Texas Instruments Incorporated

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Product Folder Link(s): PCM2912A