BLOCK DIAGRAM

Output

Buffer

GainStage

50

50

VCC

100

Settings

4 Bit

Input Threshold

Pre-Emphasis

Amplitude

RSA

RSB

RSC

RSD

LOSA

Power-On

Reset

BandgapVoltage

Referenceand

BiasCurrent

Generation

LOSB

LOSC

2-WireInterface &

ControlLogic

SDA

SCK

DIS

DIN+

DIN-

SDA

SCK

DIS

DOUT+

DOUT-

GainStage

InputBuffer

with

Selectable

Bandwidth

Offset

Cancellation

RATE0

RATE0

RATE1

RATE1

4 Bit

8 BitRegister

2 Bit

4 Bit + Select

4 Bit + Select

4 Bit + Select

4 Bit + Select

7 Bit + Select

7 Bit + Select

7 Bit + Select

7 Bit + Select

LOSD

LOSDetection

LOS

COC1

COC2

VCC

GND

4 Bit

SELRATE

7 Bit

SELLOS

ONET8501PB

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

A simplified block diagram of the ONET8501PB is shown in Figure 1.

This compact, low power 11.3 Gbps limiting amplifier consists of a high-speed data path with offset cancellation

block (DC feedback) combined with an analog settable input threshold adjust, a loss of signal detection block

using 2 peak detectors, a two-wire interface with a control-logic block and a bandgap voltage reference and bias

current generation block.

Figure 1. Simplified Block Diagram of the ONET8501PB

2

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