RM48L540 datasheet(52/152 Pages) TI1

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RM48L940

RM48L740

RM48L540

SPNS175

– SEPTEMBER 2011

www.ti.com

4.4

Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset

condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the

output buffer is implemented as an open drain (drives low only). To ensure an external reset is not

arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

4.4.1

Causes of Warm Reset

Table 4-5. Causes of Warm Reset

DEVICE EVENT

SYSTEM STATUS FLAG

Power-Up Reset

Exception Status Register, bit 15

Oscillator fail

Global Status Register, bit 0

PLL slip

Global Status Register, bits 8 and 9

Watchdog exception / Debugger reset

Exception Status Register, bit 13

CPU Reset (driven by the CPU STC)

Exception Status Register, bit 5

Software Reset

Exception Status Register, bit 4

External Reset

Exception Status Register, bit 3

4.4.2

nRST Timing Requirements

Table 4-6. nRST Timing Requirements(1)

PARAMETER

MIN

MAX

UNIT

tv(RST)

Valid time, nRST active after

1180 tc(OSC) + 1048tc(OSC)

nPORRST inactive

Valid time, nRST active (all other

8tc(VCLK)

System reset conditions)

tf(nRST)

500

2000

Filter time nRST pin;

pulses less than MIN will be

filtered out, pulses greater than

MAX will generate a reset

(1)

Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load

capacitance table.

System Information and Electrical Specifications

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