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SN65MLVD040 Datasheet(PDF) 7 Page - Texas Instruments

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Part # SN65MLVD040
Description  4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
PDF  29 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65MLVD040 Datasheet(HTML) 7 Page - Texas Instruments

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SN65MLVD040
www.ti.com
SLLS902 – FEBRUARY 2010
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Propagation delay time,
tpLH
1.3
1.9
2.4
ns
low-to-high-level output
Propagation delay time,
tpHL
1.3
1.9
2.4
ns
high-to-low-level output
tr
Differential output signal rise time
0.9
2
ns
See Figure 5
tf
Differential output signal fall time
0.9
2.2
ns
tsk(o)
Output skew
200
ps
tsk(p)
Pulse skew (|tPHL – tPLH|)
150
ps
tsk(pp)
Part-to-part skew (2)
300
ps
Period jitter, rms (1 standard
tjit(per)
2
ps
All channels switching, 125 MHz
deviation)(3)
clock input(4), see Figure 8
tjit(c-c)
Cycle-to-cycle jitter, rms(3)
9
ps
tjit(det)
Deterministic jitter(3)
290
ps
All channels switching, 250 Mbps
215–1 PRBS input(4), see Figure 8
tjit(r)
Random jitter (3)
4
ps
Enable time,
tPZH
high-impedance-to-high-level
7
ns
output
Enable time,
tPZL
7
ns
high-impedance-to-low-level output
See Figure 6
Disable time,
tPHZ
high-level-to-high-impedance
7
ns
output
Disable time,
tPLZ
7
ns
low-level-to-high-impedance output
(1)
All typical values are at 25°C and with a 3.3-V supply voltage.
(2)
tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3)
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4)
tr = tf = 0.5 ns (10% to 90%)
Copyright © 2010, Texas Instruments Incorporated
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