CPC5002 datasheet(9/14 Pages) IXYS

9 / 14 page

INTEGRATED CIRCUITS DIVISION

CPC5002

R01

www.ixysic.com

3.3 Output Drivers

Designed specifically for data and clock busses, the

output drivers have been configured for optimal

performance and behavior.

To reduce RF emissions and ringing on the output

lines the active low output drivers are slew limited. In

addition to limiting emissions, the slew limited outputs

reduce the need for external output series resistors.

Whenever the outputs are in the deasserted logic high

state, the open-drain outputs exhibit low leakage

performance while presenting a high impedance

(Hi-Z) to the load. Additionally, during power-up and

with the loss of VDD, the outputs default to the Hi-Z

deasserted state thereby ensuring signal integrity of

any bussed, open-drain signals connected to the

output pins

To maximize system design flexibility, the outputs are

tolerant of pull-up voltages greater than the CPC5002

supply voltage, VDD, provided the pull-up voltage

remains within the output’s specified voltage limits. For

example, using a 3.3V supply to power the CPC5002,

it’s outputs may be safely operated into a pull up

resistor to a supply voltage of 6.5V.

3.4 Power Supply Decoupling and Noise

Reduction

There are no special power supply decoupling

requirements for the CPC5002.

In addition, since the CPC5002 uses optical coupling

to transfer information across the barrier, no internal

clocking circuits are utilized to maintain the proper

output state. This negates the need to implement the

required special layout or noise reduction techniques

necessary to maintain EMI or RFI compliance.

Circuit Examples

4.1 Inverting and Non-Inverting Configurations

Shown below are typical inverting and non-inverting

circuit examples with the optional feed forward

capacitors used for high speed signals.

These designs assume a combined voltage drop of

3.3V across the input resistor and the LED with a

nominal input current of 1.5mA.

Figure 1. Inverting Configuration

CFWD increases instantaneous IF at LED turn-on to

reduce tPHL at VOUT .

Figure 2. Non-Inverting Configuration

For applications where the nominal total voltage drop

across the input resistor and the LED is not 3.3V it will

be necessary to adjust the input resistor’s value.

Examples of this would be different pull-up voltage

supplies and VIN sources that do not drive completely

to the supply rails.

499

3.3V

FWD

10pF

OUT

1.4k

1/2 CPC5002

Inverting: V

IN to VOUT

20pF

3.3V

OUT

1.4k

1/2 CPC5002

Non-Inverting: V

IN to VOUT

V+

499

FWD

10pF

20pF

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