TPS3895, TPS3896

TPS3897, TPS3898

SBVS172A

– JULY 2011 – REVISED SEPTEMBER 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

DESCRIPTION

TPS389wxyyyz

w is output configuration (see Table 1)

x is different delay from enable pin (see Table 1)

yyy is package designator

z is package quantity

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range (unless otherwise noted).

VALUE

MIN

MAX

UNIT

VCC

–0.3

7

V

CT

–0.3

V

ENABLE, SENSE, SENSE_OUT (push-pull)

–0.3

7

V

SENSE_OUT (open-drain)

–0.3

20

V

Current

SENSE_OUT

±10

mA

–40

+125

°C

Temperature

–65

+150

°C

Human body model (HBM)

2

kV

Charge device model (CDM)

500

V

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2)

All voltages are with respect to network ground terminal.

(3)

ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TPS389x

DRY (

µSON)

UNITS

6 PINS

Junction-to-ambient thermal resistance

293.8

Junction-to-case (top) thermal resistance

165.1

Junction-to-board thermal resistance

160.8

°C/W

Junction-to-top characterization parameter

27.3

Junction-to-board characterization parameter

65.8

Junction-to-case (bottom) thermal resistance

65.8

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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Copyright

© 2011, Texas Instruments Incorporated

Product Folder Link(s): TPS3895 TPS3896 TPS3897 TPS3898