UG-272

Evaluation Board User Guide

Rev. A | Page 6 of 12

SELECT EXTERNAL MCLK FREQUENCY

Having selected the digital interface specifics, next use the

EXTERNAL MCLK box to choose which frequency to use. The

boards are supplied with a 25 MHz general oscillator. If a different

clock source is required, the CLK1 SMB connector can be used

to supply a different MCLK value.

Two options for the general oscillator include the AEL3013

oscillators from AEL Crystals and the SG-310SCN oscillators

from Epson Electronics.

Figure 6. EXTERNAL MCLK Input

LOADING FREQUENCY AND PHASE REGISTERS

The desired output frequency and output phase can be loaded

using the inputs shown in Figure 7. Either the FREQ 0 register or

the FREQ 1 register can be loaded with frequency data. The

frequency data is loaded in megahertz, and the equivalent hex code

is shown to the right once data is entered; click Enter to load

data. Once data is loaded, the output appears on the IOUT1 and

IOUT2 pins. Similarly, either the PHASE 0 register or PHASE 1

register can be selected, and the phase data is loaded in degrees.

The analog output frequency from the AD9833 is defined by

where FREQREG is the value loaded into the selected frequency

register in decimals. This signal is phase shifted by

2π/4096 × PHASEREG

where PHASEREG is the value contained in the selected phase

register in decimals.

Figure 7. Frequency and Phase Load

FSK AND PSK FUNCTIONALITY

In software mode, the AD9833 can be set up for FSK or PSK

functionality by simply entering the bit rate in milliseconds and

selecting the push-button option (see Figure 8).

Figure 8. FSK and PSK Functionality

WAVEFORM OPTIONS

The output waveform can be selected as a sinusoidal waveform

or a ramp waveform. The internal comparator in the AD9833

can be disabled or enabled (see Figure 9). The MSB or the

MSB/2 of the phase accumulator can be selected as the output

on the SIGN BIT OUT pin.

Figure 9. Waveform Profile and SIGN BIT OUT Pin

Power-Down Options

The AD9833 has various power-down options selected through

the control register. The part can disable the MCLK or disable

the DAC if just the MSB output is used on the SIGN BIT OUT

pin, or it can power down both sections for a lower power sleep

mode (see Figure 10).

Figure 10. Power-Down Options