SN74ALS235

64 × 5 ASYNCHRONOUS FIRST IN, FIRST OUT MEMORY

SDAS108A − OCTOBER 1986 − REVISED SEPTEMBER 1993

2

POST OFFICE BOX 655303

POST OFFICE BOX 1443

description (continued)

The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high

and OR low signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see

Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until

SI goes low. If SI goes low before RST goes high, the input data will not be shifted in and IR goes high. Data

outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE)

input is high. OE does not affect the status-flag outputs (see Figure 2).

The SN74ALS235 is characterized for operation from 0

°C to 70°C.

1D

5

D0

Q0

16

6

D1

Q1

15

7

D2

Q2

14

8

D3

Q3

13

9

D4

Q4

12

FIFO 64

× 5

CTR

RST

6

4

SI

G2

R

11

OR

17

5 + /C1

18

SO

G3

4 −

EN 6

1

AF/AE

19

HF

2

IR

3

OE

CT = 0

3CT > 0

(CT > 0) G4

CT

≤ 8/CT ≥ 56

CT

≥ 32

2CT < 64

(CT < 64) G5

† This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.