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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

SN74LVCH16652A-EP

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

Complementary output-enable (OEAB and OEBA) inputs control the transceiver functions. Select-control (SAB

and SBA) inputs select whether real-time or stored data is transferred. A low input level selects real-time data,

and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding

glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the

four fundamental bus-management functions that can be performed with the SN74LVCH16652A.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the

appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable

inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the

internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output

reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of

bus lines remains at its last-level configuration.

pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is

determined by the current-sinking/current-sourcing capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or

pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input

circuit and is not disabled by OE or DIR.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40

°C to 85°C

TSSOP – DGG

Tape and reel

CLVCH16652AIDGGREP

CH16652AEP

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

INPUTS

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1–A8

B1–B8

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑

↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Store A, hold B

H

H

↑

↑

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Input

Hold A, store B

L

L

↑

↑

X

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

X

H

X

Input

Output

Stored A data to B bus

Stored A data to B bus and

H

L

H or L

H or L

H

H

Output

Output

stored B data to A bus

(1)

The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always

are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

(2)

Select control = L, clocks can occur simultaneously. Select control = H, clocks must be staggered to load both registers.

2