SN54AS877, SN74AS877

8BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS

SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985

POST OFFICE BOX 655303

POST OFFICE BOX 1443

7

switching characteristics (see Note 1)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

R1 = 500

Ω,

PARAMETER

FROM

TO

R2 = 500

UNIT

PARAMETER

(INPUT)

(OUTPUT)

TA = MIN to MAX

UNIT

SN54AS877

SN74AS877

MIN

MAX

MIN

MAX

fmax

45

50

MHz

tPLH

Any A port

Any B port

2

8.5

2

7

ns

tPHL

Any A port

Any B port

3

10.5

3

9

ns

tPLH

Any B port

Any A port

2

9

2

7.5

ns

tPHL

Any B port

Any A port

3

10.5

3

9

ns

tPLH

S0, S1, S2 †

Any A or B

2

11.5

2

10

ns

tPHL

S0, S1, S2 †

port

3

9.5

3

8

ns

tPLH

CLk

Any A or B

2

11

2

9

ns

tPHL

CLk

port

3

13

3

11.5

ns

tPLH

CLK

QB

2

10.5

2

8

ns

tPHL

CLK

QB

3

10

3

8.5

ns

tPHZ

2

7.5

2

6.5

ns

tPLZ

S0, S1, S2 †

Any A or B

3

13

3

10.5

ns

tPZH

S0, S1, S2 †

Any A or B

port

2

9

2

7

ns

tPZL

port

3

11.5

3

9.5

ns

NOTE 1: Load circuit and voltage waveforms are shown in Section 1.

† The positive transition of S2 will cause low-level data at the A output Bus or stored in the shift register to be invalid for 12 ns.