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SN74AS1821 Datasheet(PDF) 1 Page - Texas Instruments

Part # SN74AS1821
Description  10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
PDF  5 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74AS1821 Datasheet(HTML) 1 Page - Texas Instruments

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SN74AS1821
10BIT BUS INTERFACE FLIPFLOPS WITH 3STATE OUTPUTS
SDAS131 − APRIL 1987
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Copyright
1987, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all
parameters.
• Center V
CC and GND Configuration Provides
Minimum Lead Inductance in High Current
Switching Applications
• Provides Extra Data Width Necessary for Wider
Address/Data Paths or Buses with Parity
• Outputs Have Undershoot Protection Circuitry
• Power-Up High-Impedance State
• Package Options include Plastic DIPS. Use the
’AS821 for Plastic and Ceramic Chip Carriers
and “Small Outline” Package Options.
• Buffered Control inputs to Reduce DC Loading
Effects
description
This 10-bit flip-flop device features three-state
outputs designed specifically for driving highly
capacitive or relatively low-impedance loads. It is
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers. The ten flip-flops are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs on the
’AS1821 will be true.
A buffered output-control input can be used to
place the ten outputs in either a normal logic state
(high or low levels) or a high-impedance state. In
the high-impedance state the outputs neither load
nor drive the bus lines significantly.
The
high-impedance state and increased drive provide
the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components. The output control (OC)
does not affect the internal operation of the
flipflops. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
The SN74AS1821 is characterized for operation
from 0
°C to 70°C.
NT PACKAGE
(TOP VIEW)
FUNCTION TABLE
(each flip-flop)
logic symbol†
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
INPUTS
OUTPUT
LH
X
DQ
CLK
OC
QO
↑
Z
H
L
↑
L
HX
L
LL
X
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5Q
4Q
3Q
2Q
1Q
VCC
OC
1D
2D
3D
4D
5D
6Q
7Q
8Q
9Q
10Q
CLK
GND
10D
9D
8D
7D
6D
10Q
9Q
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
(20)
(21)
(22)
(23)
(24)
(1)
(2)
(3)
(4)
(5)
10D
9D
8D
7D
6D
5D
4D
3D
2D
1D
CLK
OC
(17)
(16)
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
(19)
(7)
1D
C1
EN


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