MAX7321 datasheet(3/14 Pages) MAXIM

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I2C Port Expander with Eight Push-Pull Outputs

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PORT AND TIMING CHARACTERISTICS

(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Port Output Data Valid

tPPV

≤ 100pF

µs

TIMING CHARACTERISTICS

(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Serial Clock Frequency

fSCL

400

kHz

Bus Free Time Between a STOP

and a START Condition

tBUF

1.3

µs

Hold Time (Repeated) START

Condition

tHD, STA

0.6

µs

Repeated START Condition

Setup Time

tSU, STA

0.6

µs

STOP Condition Setup Time

tSU, STO

0.6

µs

Data Hold Time

tHD, DAT

(Note 3)

0.9

µs

Data Setup Time

tSU, DAT

100

SCL Low to Data Out Valid

tVD, DAT

SCL low to SDA output valid

3.4

µs

SCL Clock Low Period

tLOW

1.3

µs

SCL Clock High Period

tHIGH

0.7

µs

Rise Time of Both SDA and SCL

Signals, Receiving

(Notes 2, 4)

20 +

0.1Cb

300

Fall Time of Both SDA and SCL

Signals, Receiving

(Notes 2, 4)

20 +

0.1Cb

300

Fall Time of SDA Transmitting

tF,TX

(Notes 2, 4)

20 +

0.1Cb

250

Pulse Width of Spike Suppressed

tSP

(Note 5)

Capacitive Load for Each Bus

Line

(Note 2)

400

RST Pulse Width

500

RST Rising to START Condition

Setup Time

tRST

1µs

Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.

Note 2: Guaranteed by design.

Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x V+ and 0.7 x V+, ISINK

≤ 6mA.

Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

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