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CXD2467Q Datasheet(PDF) 13 Page - Sony Corporation |
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CXD2467Q Datasheet(HTML) 13 Page - Sony Corporation |
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13 / 38 page ![]() – 13 – CXD2467Q Parallel Transfer Data AC Characteristics (VDD = 3.3 ± 0.3V, VSS = 0V, Topr = –20 to +75°C) Item PCTL setup time with respect to rise of PCLK PCTL hold time with respect to rise of PCLK PDAT[9:0] setup time with respect to rise of PCLK PDAT[9:0] hold time with respect to rise of PCLK PCLK pulse width tcs tch tds tdh tw Symbol 8T∗5 8T 4T 4T 4T — — — — — — — — — — Min. Typ. Max. ∗5 T: Master clock (CLK1P/CLK1N, CLK1C, CLK3P/CLK3N, CLK3C) cycle [ns] Timing Definition PCTL PCLK PDAT[9:0] tw tds 50% 50% 50% 50% 50% 50% tdh tcs tw tch VDD VDD VDD 0V 0V 0V |
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