RHF1201_11 datasheet(19/34 Pages) STMICROELECTRONICS

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RHF1201

Electrical characteristics (unchanged after 300 kRad)

Doc ID 12585 Rev 5

19/34

7.1

RHF1201 operating modes

Extra functionalities are provided to simplify the application board as much as possible. The

operating modes offered by the RHF1201 are described in Table 11.

7.1.1

Inputs

Data format select (DFSB): when set to low level (VIL), the digital input DFSB provides a

two’s complement digital output MSB. This can be of interest when performing some further

signal processing. When set to high level (VIH), DFSB provides a standard binary output

coding.

Output enable (OEB): when set to low level (VIL), all digital outputs remain active. When

set to high level (VIH), all digital output buffers are in high impedance state while the

converter goes on sampling. When OEB is set to a low level again, the data arrives on the

output with a very short Ton delay. This feature enables the chip select of the device.

Figure 11 on page 8 summarizes this functionality.

Slew rate control (SRC): when set to high level (VIH), all digital output currents are limited

to a clamp value so that any digital noise power is reduced to the minimum. When set to low

level (VIL), the output edges are twice as fast.

Table 11.

RHF1201 operating modes

Inputs

Outputs

Analog input

differential amplitude

DFSB OEB

SRC

Most significant bit

(MSB)

(VIN-VINB) above

maximum range

CLK

D11

CLK

D11 complemented

(VIN-VINB) below

minimum range

CLK

D11

CLK

D11 complemented

(VIN-VINB) within range

CLK

D11

CLK

D11 complemented

High Impedance

CLK

low slew rate

Low slew rate

CLK

high slew rate

High slew rate

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